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king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 1 - table of contents - 1. general description ________________________________ _______________________________ 2 2. features ________________________________ ________________________________ ________ 2 3. block diagram ________________________________ ________________________________ ___ 3 4. pin description ________________________________ ________________________________ __ 3 5. control registers ________________________________ ________________________________ _ 3 6. lcd power system ________________________________ _______________________________ 3 7. relationship between display data and lcd driver pins ________________________________ __ 3 8. multi - chip connection ________________________________ ____________________________ 3 9. timing chart of cascade connection ________________________________ _________________ 3 10. common connection ________________________________ ______________________________ 3 11. mixed mode connection ________________________________ ___________________________ 3 12. precautions ________________________________ ________________________________ _____ 3 13. lcd waveform ________________________________ ________________________________ __ 3 14. pin locations ________________________________ ________________________________ ____ 3 15. absolute maximum rating ________________________________ _________________________ 3 16. recommended operating conditions ________________________________ _________________ 3 17. ac/dc characteristics ________________________________ ____________________________ 3 18. application circuit for module ________________________________ ______________________ 3 19. updated record ________________________________ ________________________________ __ 3
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 2 1. general description the KD125 is a memb er of lcd driver ic series developed by king billion electronics co. it ? s a 120 - output common / segment lcd driver ic suitable for driving small/medium scale dot matrix lcd panels, used in pda or electronic dictionary. the KD125 is good as a segment driver , common driver or common/segment driver, and it can create a low power consuming, high - resolution lcd. the KD125 have eight modes can selected to set common and segment numbers by control register . the KD125 also ha s built - in analog regulator and dc/dc conv erter and they can be enabled or disabled to use external lcd power system for larger lcd panel. 2. features ? number of lcd drive outputs: 120 com/seg ? supply voltage for lcd drive: max +16v ? supply voltage for the logic system: +2.4 to +4 v ? lcd display duty se lectable by control register ? 8 lcd configurations: 0com/120seg, 32com/88seg, 48com/72seg, 64com/56seg, 80com/40seg, 96com/24seg, 112com/8seg, 120com/0seg. ? low power consumption and low output impedance ? built - in lcd voltage regulator and booster circui t (with boost ratio of 2x/3x/4x/5x/6x) ? bias configuration: 1/6 ~ 1/12 bias. ? bus width selectable: 1 - bit series / 4 - bit parallel modes. ? package: 15 4 - pin cob (pad size:80um80um, pad pitch: 95um95um). (segment mode) ? shift clock frequency 15 mhz (max.): vdd = +3.0 to + 4 v 12 mhz (max.): vdd = +2.4 to + 3.0 v ? 4 - bit parallel / serial input modes are selectable with a mode (p/s) pin ? automatic transfer function of an enable signal ? automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 88 ?b 72 ?b 56 ?b 40 ?b 24 ?b 8 or 120 bits of input data ? line latch circuits are reset when xdispoff active (common mode ) ? shift clock frequency: 4 mhz (max.)
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 3 ? built - in x - bit shift register ? available in a single mode ? y 1 - >y x single mode y x - >y 1 single mode x=32 ?b 48 ?b 64 ?b 80 ?b 96 ?b 112 ?b 120 ? shift register circuits are reset when xdispoff active ( 16 levels gray display ) ? b/w , 4 and 16 gray levels can be displayed by the pulse width modulation. 3. block diagram
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 4 4. pin description pin name i/o description y[119..0] /cmsg[119:0] o lc d driver common/segment outputs v[5:1] p power supply for lcd driver, connect a capacitor between this terminal and gnd. v 5 v 4 v 3 v 2 v 1 g n d . ? ? ? ? ? lvp p dc/dc charge pump voltage, connect a capacitor between this terminal and gnd. . lvp v 5 ? lcap1a o dc/dc charge pump converter pad . lcap1b o dc/dc charge pump converter pad . lcap2a o dc/dc charge pump converter pad . lcap2b o dc/dc charge pump converter pad . lcap3a o dc/dc charge pump converter pad . lcap4a o dc/dc charge pump converter pad . lcap5a o dc/dc charge pump converter pad . lgs1 i regulator voltage setting pin (adjust v5 voltage) lgs2 i regulator voltage setting pin (adjust v5 voltage) vag o internal reference voltage. vdd p positive power input. adding 0.1 f capacitor as by - pass capacit or on power pins is necessary.(within 1 cm distance) rstn i system reset pin .when low level active. the xrst l pulse timing min value is 200us and max value is 0.5s
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 5 pin name i/o description gnd x2 p power ground pads. di[3:0] b command/data i/o port. all these pins are in push - pull mode dio[3:0] pin is used for nibble mode data transferring. p/sn b this is the parallel data input/serial data input switch terminal. p/s=?h?: parallel data input. p/s=?l?: serial data input. l/r i input pin for selecting the reading direction of display data when set to gnd level "l", data is read sequentially from y 119 to y 0. when set to vdd level "h", data is read sequentially from y 0 to y 119. eio2, eio1 i/o input/output for chip selection at segment mode and flm input output function at com/se g mix mode or common mode. xgck i clock input for 16 level clock source xck i clock input for taking display data at segment mode xdispoff i control input for output of non - select level lp i latch pulse input for display data at segment mode/ shift clo ck input for shift register at common mode fr i ac - converting signal input for lcd drive waveform xcs i this is the command mode select pin. when xcs=?l? then write command to the lcd. sdi i the series command data input pin. sc l k i the series command clock input pin. 5. control registers there are 97 control bits used to configure the KD125. the charge - pump and current follower bias circuit are included in KD125. these 97 control bits are written by the series interface of xcs, sdi, sclk. the timin g is shown as below diagram, and the function descriptions of control bits are summarized in following table. bit[14:13] bit12 bit11 bit10 bit9 bit[8:6] bit[5:3] bit[2:0] reset value
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 6 gray[1:0] blank bufe cpumpe pdown vadj[2:0] bias[2:0] com[2:0] 0000_00 00_0000 bit[39:35] bit[34:30] bit[29:25] bit[24:20] bit[19:15] reset value gray4[4:0] gray3[4:0] gray2[4:0] gray1[4:0] gray0[4:0] 0000_0000_0000 bit[64:60] bit[59:55] bit[54:50] bit[49:45] bit[44:40] reset value gray9[4:0] gray8[4:0] gray7[4:0] gray6 [4:0] gray5[4:0] 0000_0000_0000 bit[89:85] bit[84:80] bit[79:75] bit[74:70] bit[69:65] reset value gray14[4:0] gray13[4:0] gray12[4:0] gray11[4:0] gray10[4:0] 0000_0000_0000 bit[96:95] bit[94:90] reset value cpck[1:0] gray15[4:0] 0000_0000_0000 nam e description cpck[1:0] charge pump clock select 00:32k 01:64k 10:128k 11:256k gray0[4:0] ~ gray15[4:0] the mapping register between the levels selected in shift data and the real gray scale if the content of gray1 is 0x01, when value of a certain pixel is 1 the displayed effect will correspond to actual gray level 1, the 16 gray scale display use all 16 registers gray0 ~ gray15 to select among 32 available gray levels to correspond to level 0 ~ 15 , when 4 gray scale display utilizes registers gray0 ~ g ray3 to select among 32 gray levels to correspond to level 0 ~ 15. gray[1:0] ? 00 ? : black/white display. ? 01 ? : 4 levels gray display. ? 10 ? :16 levels gray display. ? 11 ? :reserved b lank 0: n ormal d isplay 1: lcd display blanked. the com signal s of lcd driver output inactive levels (v4
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 7 nam e description and v1) while seg signal s output normal display patterns . pdown 1:lcd charge pump disable 0:lcd charge pump enable bufe 1: disable internal bias network buffer, lv1~5 are provided externally. 0: enable internal bias network buf fer. cpumpe 1: internal charge - pump is disabled and lcd power is supplied externally. 0: internal charge - pump is enabled. vadj[2:0] lcd contrast adjustment ( ? 10%) ? 111 ? : - 10% darkest, ? 110 ? : - 7% ? 101 ? : - 4% ? 100 ? : - 1% ? 011 ? :+1% ? 010::+4% ? 001 ? :+7% ? 000 ? : +10 % lightest. bias[2:0] lcd power system bias configuration ? 000 ? : reserved ? 001 ? : 1/6 bias ? 010 ? : 1/7 bias ? 011 ? : 1/8 bias ? 100 ? : 1/9 bias ? 101 ? : 1/10 bias ? 110 ? : 1/11 bias ? 111 ? :1/12 bias com[2:0] lcd com/seg output configuration mode ? 000 ? : 1 28 seg ? 00 1 ? : 32 c om 88 seg ? 010 ? : 48 com 72 seg ? 011 ? : 64 com 56 seg ? 100 ? : 80 com 40 seg
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 8 nam e description ? 101 ? : 96 com 24 seg ? 110 ? : 112 com 8 seg ? 111 ? : 120 com 1 2 3 4 5 6 7 92 93 sclk xcs sdi control register write timing bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 91 bit92 bit 93 bit 94 bit 95 bit 96 94 95 96 97 6. lcd power system the internal regulator, charge - pump and current follower b ias circuits are built in to provide the lcd power system, when the internal lcd power system is used by set cpumpe and bufe bits. if the external lcd power is provided, the internal lcd power system shall be disabled by clear the cpumpe bit. the following table shows the relationship of lcd power system. bit[14:13 ] bit12 bit11 bit10 bit9 bit[8:6] bit[5:3] bit[2:0] reset value gray[1:0] blan k buf e cpump e pdow n vadj[2:0 ] bias[2:0 ] com[2:0 ] 0000_0000_000 0 pdown cpumpe bufe function 0 0 0 i nternal charge - pump and current follower bias circuit are enabled to supply the lcd display power. 0 0 1 i nternal charge - pump system is enabled, but the current follower bias circuit is disabled, and the external power sources are applied lv5~lv1. 0 1 0 i nternal charg e - pump system is disabled, but the current follower bias circuit
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 9 is enabled. the single external power is applied to lvp, and internal bias circuit will generate the lv5~lv1 voltages. 0 1 1 i nternal charge - pump and current follower bias circuit are disabl ed, and the external power sources are applied to lvp and lv5~lv1 pads. 1 0 0 the lcd power system is disable, but the lvp is applied to vdd and lv5~lv1 is applied to high impedance. 1 0 1 the lcd power system is disable, but the lvp is applied to vdd and lv5~lv1 is applied to high impedance. 1 1 0 the lcd power system is disable, but the lvp and lv5~lv1 is applied to high impedance. 1 1 1 the lcd power system is disable, but the lvp and lv5~lv1 is applied to high impedance. the boost circuit ch arge pump regulated voltage to lcd highest voltage lvp (3~6 times of vdd voltage).the set - up voltage generated at lvp output the v5 through the voltage regulator circuit. the lcd voltage(v5) can also be fine - tuned (in ? 10% range) through the vadj[2:0] bit s. the lcd voltage levels v1~v5 shall be configured properly by the bias[2:0] bits based on the lcd duty and lcd highest voltage. the following table is a general configuration relationship for the lcd duty and bias. duty bias 1/32 1/6 or 1/7 1/48 1/7 o r 1/8 1/64 1/8 or 1/9 1/80 1/8 or 1/9 1/96 1/9 or 1/10 1/112 1/10 or 1/11 1/120 1/11 or 1/12 voltage charge pump: the vdd voltage is then boosted up by 3, 4, 5, or 6 times to generate lvp, depending on external c apacitor s configurations as shown bel ow. please note that l v p must be lower than maximum operation voltage to prevent chip from break - down. the capacitance of capacitors connected to lvp and v1~v5 shall be increased in an appropriate amount based on the lcd panel size. f or small size
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 10 lcd pane l, the 0.1uf capacitors are enough, but (1uf~10uf) or bigger capacitors may be necessary for larger lcd size application.. . the setup - up voltage circuits i2 r1 i1 r2 i26 r1 i27 r2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag gnd gnd lvp=4xvdd=12v 4x set-up voltage circuit vdd=3v gnd lvp=3xvdd=9v vdd=3v gnd 3x set-up voltage circuit
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 11 i37 r1 i38 r2 i2 r1 i1 r2 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 c1 c2 c2 c2 c2 c2 c2 c2 c2 c1 c1 c1 c1 v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag gnd gnd lvp=6xvdd=15v vdd=2.5v 6x set-up voltage circuit lvp=5xvdd=15v 5x set-up voltage circuit gnd vdd=3v gnd c1 and c2 are determined by the size of the lcd being driven ( 0.1u~10u) . the voltage regulator ci rcuit: vadj[2:0] adj 000 +10% 001 +7% 010 +4% 011 +1% 100 - 1% 101 - 4% 110 - 7% 111 - 10% v5=(1+r2/r1)*(1v ? vref * adj) charge pump times vref 6x 1.7 5x 1.2 4x 1.2 condition : vdd = 3.3v
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 12 3x 1.2 use lvp (external power) 0.9 the r1 resistor is connected between lgs2 and ground and r2 is connected to lgs1 and lgs2. lgs1 pin is sensitive to noise. vref will change if lgs1 pin is coupled with noise. please take care in pcb layout . the metal wire between lgs1 to r1 r2 resistor is as short as poss ible. 7. relationship between display data and lcd driver pins 16 - level gray scale display with pwm display data di[3] di[2] di[1] di[0] gray scale register 0 0 0 0 gray0(gray level0) 0 0 0 1 gray1(gray level1) 0 0 1 0 gray2(gray level2) 0 0 1 1 gray3 (gray level3) 0 1 0 0 gray4(gray level4) 0 1 0 1 gray5(gray level5) 0 1 1 0 gray6(gray level6) 0 1 1 1 gray7(gray level7) 1 0 0 0 gray8(gray level8) 1 0 0 1 gray9(gray level9) 1 0 1 0 gray10(gray level10) 1 0 1 1 gray11(gray level11) 1 1 0 0 gray1 2(gray level12) 1 1 0 1 gray13(gray level13) 1 1 1 0 gray14(gray level14) 1 1 1 1 gray15(gray level15) 4 - level gray scale display with pwm display data di[3]/di[1] di[2]/di[0] gray scale register 0 0 gray0(gray level0) 0 1 gray1(gray level1) 1 0 gray2(gray level2) 1 1 gray3(gray level3) - gray scale register of 32 pwm (pulse width modulate ) dec gray scale register(5 bit) pwm note 0 00000 0 brighter 1 00001 2/32 2 00010 3/32 3 00011 4/32 4 00100 5/32 5 00101 6/32 ? . ?? .
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 13 ? . ?? . ? . ?? . ? . ?? . 28 11100 29/32 29 11101 30/32 30 11110 31/32 31 11111 1 darker segment mode black/white display (4 - bit parallel input mode) number of clocks l/r eio 1 eio 2 data input 30 clock 29 clock 28 clock ? 3 clock 2 clock 1 clock di[0] y0 y4 y8 ? y108 y112 y116 di[1] y1 y5 y9 ? y109 y113 y117 di[2] y2 y6 y10 ? y110 y114 y118 l o utput input di[3] y3 y7 y11 ? y111 y115 y119 di[0] y119 y115 y111 ? y11 y7 y3 di[1] y118 y114 y110 ? y10 y6 y2 di[2] y117 y 113 y109 ? y9 y5 y1 h input output di[3] y116 y112 y108 ? y8 y4 y0 black/white display (1 - bit series input mode) number of clocks l/r eio 1 eio 2 data input 120 clock 119 clock 118 clock ? 3 clock 2 clock 1 clock di[0] y0 y1 y2 ? y117 y118 y119 di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 y118 y117 ? y2 y1 y0 di[1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x x : don't care, should be fixed to "h" or "l", avoiding floating. 4 levels gray display (4 - bit parallel input mode) number of clocks l/r eio 1 eio 2 data input 60 clock 59 clock 58 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y2 (0) y4 (0) ? y114 (0) y116 (0) y118 (0) l output input di[1] y0 (1)* y2 (1) y4 (1) ? y114 (1) y116 (1) y118 (1)
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 14 di[2] y1 (0) y3 (0) y5 (0) ? y115 (0) y117 (0) y119 (0) di[3] y1 (1) y3 (1) y5 (1) ? y115 (1) y117 (1) y119 (1) di[0] y119 (0) y117 (0) y115 (0) ? y5 (0) y3 (0) y1 (0) di[1] y119 (1) y117 (1) y115 ( 1) ? y5 (1) y3 (1) y1 (1) di[2] y118 (0) y116 (0) y114 (0) ? y4 (0) y2 (0) y0(0) h input output di[3] y118 (1) y116 (1) y114 (1) ? y4 (1) y2 (1) y0(1) (1): 2 nd bit, msb; (0): 1 st bit, lsb. 4 levels gray display (1 - bit series input mode) number of clocks l/r eio 1 eio 2 data input 240 clock 239 clock 238 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y0 (1)* y1 (0) ? y118 (1) y119 (0) y119 (1) di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 (0) y119 (1) y118 (0) ? y1 (1) y0 (0) y0 (1) di[1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x (1): 2 nd bit, msb; (0): 1 st bit, lsb. x : don't care, should be fixed to "h" or "l", avoiding floating. 16 levels gray display (4 - bit parallel input mode) number of clocks l/r eio 1 eio 2 data input 120 clock 119 clock 118 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y1 (0) y2 (0) ? y117 (0) y118 (0) y119 (0) di[1] y0 (1)* y1 (1) y2 (1) ? y117 (1) y118 (1) y119 (1) di [2] y0 (2)* y1 (2) y2 (2) ? y117 (2) y118 (2) y119 (2) l output input di[3] y0 (3)* y1 (3) y2 (3) ? y117 (3) y118 (3) y119 (3) di[0] y119 (0) y118 (0) y117 (0) ? y2 (0) y1 (0) y0 (0) di[1] y119 (1) y118 (1) y117 (1) ? y2 (1) y1 (1) y0 (1) di[2 ] y119 (2) y118 (2) y117 (2) ? y2 (2) y1 (2) y0 (2) h input output di[3] y119 (3) y118 (3) y117 (3) ? y2 (3) y1 (3) y0 (3) (3): 4 th bit, msb; (2): 3 rd bit; (1): 2 nd bit; (0): 1 st bit, lsb. 16 levels gray display (1 - bit series input mode) n umber of clocks l/r eio 1 eio 2 data input 480 clock 479 clock 478 clock ? 3 clock 2 clock 1 clock
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 15 di[0] y0 (0)* y0 (1)* y0 (2)* ? y119 (1) y119 (2) y119 (3) di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 (0) y 119 (1) y119(2) ? y0 (1) y0 (2) y0 (3) di[1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x (3): 4 th bit, msb; (2): 3 rd bit; (1) 2 nd bit; (0): 1 st bit, lsb. x : don't care, should be fixed to "h" or "l", avoiding floating. common mode l /r data transfer direction eio1 eio2 l y 119 y 0 output input h y 0 y 119 input output mixed mode (common/segment mode) for example : when (sel2, sel1, sel0) = (0, 0, 1) , s elect the 32 com/88 seg mode , then segment side of mixed mode. black/white displ ay (4 - bit parallel input mode) number of clocks l/r eio 1 eio 2 data input 22 clock 21 clock 20 clock ? 3 clock 2 clock 1 clock di[0] y0 y4 y8 ? y76 y80 y84 di[1] y1 y5 y9 ? y77 y81 y85 di[2] y2 y6 y10 ? y78 y82 y86 l output input di[3] y3 y7 y11 ? y79 y83 y87 di[0] y119 y115 y111 ? y43 y39 y35 di[1] y118 y114 y110 ? y42 y38 y34 di[2] y117 y113 y109 ? y41 y37 y33 h input output di[3] y116 y112 y108 ? y40 y36 y32 black/white display (1 - bit series input mode) number of clocks l/r eio 1 eio 2 data input 88 clock 87 clock 86 clock ? 3 clock 2 clock 1 clock
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 16 di[0] y0 y1 y2 ? y85 y86 y87 di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 y118 y117 ? y34 y33 y32 di[ 1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x x : don't care, should be fixed to "h" or "l", avoiding floating. 4 levels gray display (4 - bit parallel input mode) number of clocks l/r eio 1 eio 2 data input 44 clock 43 clock 42 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y2 (0) y4 (0) ? y82 (0) y84 (0) y86 (0) di[1] y0 (1)* y2 (1) y4 (1) ? y82 (1) y84 (1) y86 (1) di[2] y1 (0) y3 (0) y5 (0) ? y83 (0) y85 (0) y87 (0) l output input di[3] y1 (1) y3 (1) y5 (1) ? y83 (1) y85 (1) y87 (1) di[0] y119 (0) y117 (0) y115 (0) ? y37 (0) y35 (0) y33 (0) di[1] y119 (1) y117 (1) y115 (1) ? y37 (1) y35 (1) y33 (1) di[2] y118 (0) y116 (0) y114 (0) ? y36 (0) y34 (0) y32 (0) h input output di[3] y118 (1) y116 (1) y114 (1) ? y36 (1) y34 (1) y32 (1) (1): 2 nd bit, msb; (0): 1 st bit, lsb. 4 levels gray display (1 - bit series input mode) number of clocks l/r eio 1 eio 2 data input 176 clock 175 clock 174 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y0 (1)* y1 (0) ? y86 (1) y87 (0) y87 (1) di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 (0) y119 (1) y118 (0) ? y33 (1) y32 (0) y32 (1) di[1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x (1): 2 nd b it, msb; (0): 1 st bit, lsb. x : don't care, should be fixed to "h" or "l", avoiding floating. 16 levels gray display (4 - bit parallel input mode)
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 17 number of clocks l/r eio 1 eio 2 data input 88 clock 87 clock 86 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y1 (0) y2 (0) ? y85 (0) y86 (0) y87 (0) di[1] y0 (1)* y1 (1) y2 (1) ? y85 (1) y86 (1) y87 (1) di[2] y0 (2)* y1 (2) y2 (2) ? y85 (2) y86 (2) y87 (2) l output i nput di[3] y0 (3)* y1 (3) y2 (3) ? y85 (3) y86 (3) y87 (3) di[0] y 119 (0) y118 (0) y117 (0) ? y34 (0) y33 (0) y32 (0) di[1] y119 (1) y118 (1) y117 (1) ? y34 (1) y33 (1) y32 (1) di[2] y119 (2) y118 (2) y117 (2) ? y35 (2) y33 (2) y32 (2) h input output di[3] y119 (3) y118 (3) y117 (3) ? y35 (3) y33 (3) y32 (3) (3): 4 th bit, msb; (2): 3 rd bit; (1): 2 nd bit; (0): 1 st bit, lsb. 16 levels gray display (1 - bit series input mode) number of clocks l/r eio 1 eio 2 data input 352 clock 351 clock 350 clock ? 3 clock 2 clock 1 clock di[0] y0 (0)* y0 (1)* y0 (2)* ? y87 (1) y87 (2) y87 (3) di[1] x x x x x x x di[2] x x x x x x x l output input di[3] x x x x x x x di[0] y119 (0) y119 (1) y119(2) ? y32 (1) y32 (2) y32 (3) di[1] x x x x x x x di[2] x x x x x x x h input output di[3] x x x x x x x (3): 4 th bit, ms b; (2): 3 rd bit; (1) 2 nd bit; (0): 1 st bit, lsb. x : don't care, should be fixed to "h" or "l", avoiding floating. common side of mixed mode l/r data transfer direction eio 1 eio 2 l y 119 y 88 seg_end output input h y 0 y 119 input seg_end output
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 18 8. multi - chip connection
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 19 9. timing chart of cascade connection
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 20 10. common connection
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 21 11. mixed mode connection
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 22
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 23 12. precaution s precautions when connecting or disconnecting the power supply this ic has a high - voltage lcd driver, so a high current that may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating may permanently damage it. the details are as follows, w hen connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lcd drive power and when connecting the logic power supply, the logic condition of this ic inside is insecure. therefore connect the lcd drive power suppl y after resetting logic condition of this ic inside on /dispoff function. after that, cancel the /dispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level vss on /dispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here 13. lcd waveform fr lp . . . // // . . . frame period frame period
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 24 1st frame seg waveform com waveform 2nd frame 3rd frame gnd lv1 lv2 lv3 lv4 lv5 gnd lv1 lv2 lv3 lv4 lv5 type b lcd com and seg waveform seg waveform gnd lv1 lv2 lv3 lv4 lv5 type b lcd com/seg waveform 1st frame 2nd frame 3rd frame
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 25 14. pin locations 1 cmsg[31] x= - 3618 y= 420 79 cmsg[10 9] x= 3618.05 y= - 437 2 cmsg[30] x= - 3618 y= 325 80 cmsg[108] x= 3618.05 y= - 342 3 cmsg[29] x= - 3618 y= 230 81 cmsg[107] x= 3618.05 y= - 247 4 cmsg[28] x= - 3618 y= 135 82 cmsg[106] x= 3618.05 y= - 152 5 cmsg[27] x= - 3618 y= 39.5 83 cmsg[105] x= 3618.05 y = - 57 6 cmsg[26] x= - 3618 y= - 55.5 84 cmsg[104] x= 3618.05 y= 38 7 cmsg[25] x= - 3618 y= - 151 85 cmsg[103] x= 3618.05 y= 133 8 cmsg[24] x= - 3618 y= - 246 86 cmsg[102] x= 3618.05 y= 228 9 cmsg[23] x= - 3618 y= - 341 87 cmsg[101] x= 3618.05 y= 323 10 cmsg[2 2] x= - 3618 y= - 436 88 cmsg[100] x= 3618.05 y= 418 11 cmsg[21] x= - 3264.9 y= - 819 89 cmsg[99] x= 3219.9 y= 819 12 cmsg[20] x= - 3169.9 y= - 819 90 cmsg[98] x= 3124.9 y= 819 13 cmsg[19] x= - 3074.9 y= - 819 91 cmsg[97] x= 3029.9 y= 819 14 cmsg[18] x= - 2979. 9 y= - 819 92 cmsg[96] x= 2934.9 y= 819 15 cmsg[17] x= - 2884.9 y= - 819 93 cmsg[95] x= 2839.9 y= 819 16 cmsg[16] x= - 2789.9 y= - 819 94 cmsg[94] x= 2744.9 y= 819 17 cmsg[15] x= - 2694.9 y= - 819 95 cmsg[93] x= 2649.9 y= 819 18 cmsg[14] x= - 2599.9 y= - 819 96 cmsg[92] x= 2554.9 y= 819 19 cmsg[13] x= - 2504.9 y= - 819 97 cmsg[91] x= 2459.9 y= 819 20 cmsg[12] x= - 2409.9 y= - 819 98 cmsg[90] x= 2364.9 y= 819 21 cmsg[11] x= - 2314.9 y= - 819 99 cmsg[89] x= 2269.9 y= 819 22 cmsg[10] x= - 2219.9 y= - 819 100 cmsg[88] x = 2174.9 y= 819 23 cmsg[9] x= - 2124.9 y= - 819 101 cmsg[87] x= 2079.9 y= 819 24 cmsg[8] x= - 2029.9 y= - 819 102 cmsg[86] x= 1984.9 y= 819 25 cmsg[7] x= - 1934.9 y= - 819 103 cmsg[85] x= 1889.9 y= 819 26 cmsg[6] x= - 1839.9 y= - 819 104 cmsg[84] x= 1794.9 y= 819 27 cmsg[5] x= - 1744.9 y= - 819 105 cmsg[83] x= 1699.9 y= 819 28 cmsg[4] x= - 1649.9 y= - 819 106 cmsg[82] x= 1604.9 y= 819 29 cmsg[3] x= - 1554.9 y= - 819 107 cmsg[81] x= 1509.9 y= 819 30 cmsg[2] x= - 1459.9 y= - 819 108 cmsg[80] x= 1332.9 y= 819 31 cmsg [1] x= - 1364.9 y= - 819 109 cmsg[79] x= 1237.9 y= 819 32 cmsg[0] x= - 1269.9 y= - 819 110 cmsg[78] x= 1142.9 y= 819 33 vssa x= - 1101.4 y= - 819 111 cmsg[77] x= 1047.9 y= 819 34 lvl1 x= - 1001.1 y= - 819 112 cmsg[76] x= 952.9 y= 819 35 lvl2 x= - 906.12 y= - 819 113 cmsg[75] x= 857.9 y= 819 36 lvl3 x= - 811.12 y= - 819 114 cmsg[74] x= 762.9 y= 819 37 lvl4 x= - 716.12 y= - 819 115 cmsg[73] x= 667.9 y= 819 38 lvl5 x= - 621.12 y= - 819 116 cmsg[72] x= 572.9 y= 819
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 26 39 lvp x= - 526.12 y= - 819 117 cmsg[71] x= 477.9 y= 819 40 lcap1a x= - 431.12 y= - 819 118 cmsg[70] x= 382.9 y= 819 41 lcap1b x= - 336.12 y= - 819 119 cmsg[69] x= 287.9 y= 819 42 lcap2a x= - 241.12 y= - 819 120 cmsg[68] x= 192.9 y= 819 43 lcap2b x= - 146.12 y= - 819 121 cmsg[67] x= 97.9 y= 819 44 lcap3a x= - 51.12 y= - 819 122 cmsg[66] x= 2.9 y= 819 45 lcap4a x= 43.88 y= - 819 123 cmsg[65] x= - 92.1 y= 819 46 lcap5a x= 138.88 y= - 819 124 cmsg[64] x= - 187.1 y= 819 47 lgs1 x= 233.88 y= - 819 125 cmsg[63] x= - 282.1 y= 819 48 lgs2 x= 328.88 y= - 819 126 cmsg[62] x= - 377 .1 y= 819 49 vag x= 423.88 y= - 819 127 cmsg[61] x= - 472.1 y= 819 50 vdd x= 525.13 y= - 819 128 cmsg[60] x= - 567.1 y= 819 51 rstn x= 620.13 y= - 819 129 cmsg[59] x= - 662.1 y= 819 52 di[3] x= 715.13 y= - 819 130 cmsg[58] x= - 757.1 y= 819 53 di[2] x= 810.13 y= - 819 131 cmsg[57] x= - 852.1 y= 819 54 di[1] x= 906.38 y= - 819 132 cmsg[56] x= - 947.1 y= 819 55 di[0] x= 1000.13 y= - 819 133 cmsg[55] x= - 1042.1 y= 819 56 p_sn x= 1095.13 y= - 819 134 cmsg[54] x= - 1137.1 y= 819 57 l_r x= 1190.13 y= - 819 135 cmsg[53] x= - 1232.1 y= 819 58 eio1 x= 1285.13 y= - 819 136 cmsg[52] x= - 1327.1 y= 819 59 eio2 x= 1380.13 y= - 819 137 cmsg[51] x= - 1422.1 y= 819 60 clk32 x= 1480.6 y= - 819 138 cmsg[50] x= - 1517.1 y= 819 61 xck x= 1575.6 y= - 819 139 cmsg[49] x= - 1612.1 y= 819 62 xdispoff x= 1670.6 y= - 819 140 cmsg[48] x= - 1707.1 y= 819 63 lp x= 1765.6 y= - 819 141 cmsg[47] x= - 1802.1 y= 819 64 fr x= 1860.6 y= - 819 142 cmsg[46] x= - 1897.1 y= 819 65 xcs x= 1955.6 y= - 819 143 cmsg[45] x= - 1992.1 y= 819 66 sdi x= 2050.6 y= - 819 144 cmsg[44] x= - 2087.1 y= 819 67 sclk x= 2145.6 y= - 819 145 cmsg[43] x= - 2182.1 y= 819 68 gnd x= 2240.6 y= - 819 146 cmsg[42] x= - 2277.1 y= 819 69 cmsg[119] x= 2409.1 y= - 819 147 cmsg[41] x= - 2372.1 y= 819 70 cmsg[118] x= 2504.1 y= - 819 148 cmsg[40] x= - 2 467.1 y= 819 71 cmsg[117] x= 2599.1 y= - 819 149 cmsg[39] x= - 2562.1 y= 819 72 cmsg[116] x= 2694.1 y= - 819 150 cmsg[38] x= - 2657.1 y= 819 73 cmsg[115] x= 2789.1 y= - 819 151 cmsg[37] x= - 2752.1 y= 819 74 cmsg[114] x= 2884.1 y= - 819 152 cmsg[36] x= - 2847. 1 y= 819 75 cmsg[113] x= 2979.1 y= - 819 153 cmsg[35] x= - 2942.1 y= 819 76 cmsg[112] x= 3074.1 y= - 819 154 cmsg[34] x= - 3037.1 y= 819 77 cmsg[111] x= 3169.1 y= - 819 155 cmsg[33] x= - 3132.1 y= 819 78 cmsg[110] x= 3264.1 y= - 819 156 cmsg[32] x= - 3227.1 y= 819
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 27 15. absolute maximum rating item sym. rating condition supply voltage v dd - 0.5v ~ 4v input voltage v in - 0.5v ~ v dd +0.5v output voltage v o - 0.5v ~ v dd +0.5v operating temperature t op 0 c ~ 70 c storage temperature t st - 50 c ~ 100 c 16. recommende d operating conditions item sym. rating condition supply voltage v dd 2.4v ~ 4v lcd operating voltage v v5 < 16v v ih 0.9 v dd ~ v dd input voltage v il 0.0v ~ 0.1v dd operating temperature t op 0 c ~ 70 c storage temperature t st - 50 c ~ 100 c
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 28 17. ac / dc characteristics test condition: t emperature: 25 j , vdd : 3v ? 10% p arameters symbol m in. t yp. max. unit condition supply c urrent i d d 300 350 g a standby m ode c urrent i stby 1 g a input h igh v oltage v i h 0.8 v dd i nput pins input l ow v oltage v i l 0.2 v dd i nput pins input leakage c urrent i i l 20 g a v il = gnd , vdd input h ysteresis w idth v hys 1/3 v dd input pins threshold=2/3v dd (input from low to high) threshold=1/3v dd (input from high to low) output source c urrent i o h 2 .0 ma rd[7..0 ] , v ol =2.0v output s ink c urrent i o l 2 .0 ma rd[7..0 ] , v ol =0.4v 18. app lication circuit for module
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 29 i37 r1 i38 r2 c1 c1 c1 c1 c1 c2 c2 c2 c2 c2 c2 c2 c2 di[3:0] eio1 eio2 fr l/r lp p/sn sclk sdi xck xcs xdispoff xgck v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag y[119:0] di[3:0] eio1 eio2 fr l/r lp p/sn sclk sdi xck xcs xdispoff xgck v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag y[119:0] di[3:0] eio1 eio2 fr l/r lp p/sn sclk sdi xck xcs xdispoff xgck v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag y[119:0] com[119:0] lvp di[3:0] lgs2 xck vdd lgs1 vdd v5 flm v4 xgck v3 xidspoff v2 lp fr v1 xcs0 lcap2b sdi lcap1b sclk lcap5a lcap4a seg[119:0] lcap3a lcap2a lcap1a seg[239:120] gnd v1 v2 v3 v4 v5 lvp v1 v2 v3 v4 v5 lvp sclk sdi xcs1 fr lp xidspoff xgck gnd vdd vdd xck di[3:0] sclk sdi xcs1 fr lp xidspoff xgck eio3 vdd vdd xck di[3:0] 120 com x 240 seg from lcd control
king bil lion electronics co., ltd a@ ?? 1q l a? |3 -- ? q KD125 lcd driver series january 20, 2005 v 1. 1 0 this specification is subject to change without notice. please contact sales p erson for the latest version before use. 30 i37 r1 i38 r2 c1 c1 c1 c1 c2 c2 c2 c2 c2 c2 c2 c2 di[3:0] eio1 eio2 fr l/r lp p/sn sclk sdi xck xcs xdispoff xgck v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag y[119:0] di[3:0] eio1 eio2 fr l/r lp p/sn sclk sdi xck xcs xdispoff xgck v1 v2 v3 v4 v5 lcap1a lcap1b lcap2a lcap2b lcap3a lcap4a lcap5a lgs1 lgs2 lvp vag y[119:0] com[111:0] seg[7:0],com[111:0] lvp di[3:0] lgs2 xck vdd lgs1 vdd v5 flm v4 xgck v3 xidspoff v2 lp fr v1 xcs0 lcap2b sdi lcap1b sclk lcap4a seg[7:0] lcap3a lcap2a lcap1a seg[127:8] gnd v1 v2 v3 v4 v5 lvp sclk sdi xcs1 fr lp xidspoff xgck eio2 vdd vdd xck di[3:0] 112 com x 128 seg from lcd control 19. updated record version date update history v1.0 12/9/2004 first release version v1. 1 1 9 / 1 /200 5 modify setup - up voltage circuits and application circuit. add a capacitor between lgs1 and gnd.

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